Manufacturing process of element chip using laser grooving and plasma-etching

ABSTRACT

A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

CROSS REFERENCE TO RELATED APPLICATION

The present application is based on and claims priority under 35 U.S.C.§ 119 with respect to the Japanese Patent Application No. 2018-061672filed on Mar. 28, 2018, of which entire content is incorporated hereinby reference into the present application.

TECHNICAL FIELD

The present invention relates to a manufacturing process of an elementchip, and in particular to the manufacturing process of the element chipincluding a laser grooving step and a dicing step with a plasmaexposure.

BACKGROUND

The element chips are produced by individualizing or dicing a substrateincluding a semiconductor layer and a wiring layer, for example.Typically, the substrate contains a plurality of element regions anddicing regions defining the element regions, in which the dicing regionsare removed to form the element chips from the substrate. PatentDocument 1 (JPA 2005-064231) discloses a method for dividing aplate-like workpiece, which includes dicing the substrate along thedicing regions by laser scribing (laser grooving) a portion of thesubstrate along dicing regions and cutting off the remaining portion ofthe substrate with a cutting blade.

The laser grooving step often uses a pulsed laser beam for suppressing athermal impact on the substrate. It is known that a laser ablation makesmaterials composing the substrate on a target of the laser beamscattering as fine particles called as debris, which in turn adhere tothe surface of the substrate in the laser grooving step. However, whenthe remaining portion of the substrate is mechanically cut off after thelaser grooving step as taught in Patent Document 1, the debris on thedicing regions of the substrate substantially gives no influence on aproduction quality of the element chips.

Meantime, a plasma-dicing step for dicing the substrate has recentlybeen proposed, in which after laser-scribing a portion of the substrate,a plasma-dicing step is used for etching the remaining portion along thedicing regions by exposing the substrate within a plasma atmosphere. Thesource gas and the condition for generating the plasma atmosphere aremodified in accordance with the material and a thickness of the materialto be processed. Therefore, the flatness and the composition of thedebris along the dicing regions give a substantial impact on theproduction quality of the element chips in the plasma-etching step.

SUMMARY

One aspect of the present invention relates to a manufacturing processof an element chip, which comprises a preparing step for preparing asubstrate having first and second sides opposed to each other, thesubstrate containing a semiconductor layer, a wiring layer and a resinlayer formed on the first side, and the substrate including a pluralityof dicing regions and element regions defined by the dicing regions; alaser grooving step for irradiating a laser beam onto the dicing regionsto form grooves so as to expose the semiconductor layer along the dicingregions; and a dicing step for plasma-etching the semiconductor layeralong the dicing regions through the second side to divide the substrateinto a plurality of the element chips, wherein the laser grooving stepincludes a melting step for melting a surface of the semiconductor layerexposed along the dicing regions.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart illustrating some steps of a manufacturing processof an element chip according to a first embodiment of the presentinvention.

FIG. 2A is a top plan view of a substrate which is an object to beprocessed, and FIG. 2B is a cross-sectional view taken along a line X-Xof FIG. 2A.

FIG. 3A is an enlarged top plan view schematically illustrating aportion of the substrate, and FIG. 3B is a cross-sectional view takenalong a line Y-Y of FIG. 3A.

FIGS. 4A-4C are schematic cross-sectional views of the substrate showinga laser grooving step of the manufacturing process according to a firstembodiment.

FIG. 5 is a perspective view schematically illustrating a structure of alaser processing machine of the embodiment according to the presentinvention.

FIG. 6A is a photograph of a top side of the substrate after a firststep of the manufacturing process according to the first embodiment ofthe present invention.

FIG. 6B is a photograph of the top side of the substrate after a secondstep of the manufacturing process according to the first embodiment ofthe present invention.

FIG. 7 is a photograph of the top side of the substrate after a cleaningstep of the manufacturing process according to the first embodiment ofthe present invention.

FIGS. 8A and 8B are schematic cross-sectional views of the substrateshowing an individualizing or dicing step of the manufacturing processaccording to the embodiment.

FIG. 9A is a top plan view schematically illustrating a conveyingcarrier and the substrate held thereon according to the embodiment, andFIG. 9B is a cross-sectional view taken along a line Z-Z of FIG. 9A.

FIG. 10 is a conceptual view depicting a schematic structure in a crosssection of a plasma processing apparatus of the embodiment according tothe present invention.

FIG. 11 is a flowchart illustrating some steps of a manufacturingprocess of an element chip according to a second embodiment of thepresent invention.

FIGS. 12A-12D are schematic cross-sectional views of the substrateshowing the laser grooving step of the manufacturing process accordingto a second embodiment.

FIG. 13 is a flowchart illustrating some steps of a manufacturingprocess of an element chip according to a third embodiment of thepresent invention.

FIG. 14 is a top plan view schematically illustrating a portion of thesubstrate showing a second step of the manufacturing process accordingto a fourth embodiment.

DETAILED DESCRIPTION

With reference to attached drawings, a manufacturing process of anelement chip according to embodiments of the present invention will bedescribed hereinafter. In the description, a couple of terms forindicating the directions (for example, “upper” and “vertical”) areconveniently used just for facilitating clear understandings, it shouldnot be interpreted that those terms limit the scope of the presentinvention. Also, in the drawings, each component of the element chip isillustrated in a relative manner in size for clarifying the shape andthe feature thereof, and not necessary in the exact scale.

A substrate to be processed contains a semiconductor layer, a wiringlayer (an insulating layer), and a resin layer thereon, and thesubstrate includes a plurality of dicing regions and element regionsdefined by the dicing regions. A manufacturing process of an elementchip generally comprises steps of preparing the substrate, a lasergrooving step for irradiating a laser beam onto the substrate along thedicing regions to form grooves, and a dicing step for plasma-etching theexposed semiconductor layer.

In the laser grooving step, all of the resin layer and the wiring layerare removed along the dicing regions, and a portion of the semiconductorlayer may be removed along the dicing regions. The present disclosuresuggests homogenizing or planarizing a bottom surface of a trench orgroove along the dicing regions prior to the plasma-dicing step, which,in turn, facilitates the plasma-dicing step to be implemented in areliable and efficient manner so that desired element chips of highquality can be produced.

Typically, the insulating layer often includes Test Element Groups(TEGs) and metal wires (which may collectively be referred to as metalmaterials) along the dicing regions. Such metal materials have varietyof sizes, components, shapes, and thickness. Meanwhile, in order toincrease a productivity, a laser beam is often irradiated at a constantintensity to scribe the resin layer and the wiring layer alongirradiation preset-lines in the dicing regions. Thus, the laser beam isirradiated under such a condition required to remove the metal materialswhich are most difficult to be removed (i.e., which are large and thick,or has a low absorption rate of the laser beam). In this instance, thebeam intensity of the laser beam is much greater than that required forremoving the insulating layer.

In the disclosure, an area where the metal material is provided in thewiring layer along the dicing region is referred to as a metalcontaining area, while another area where no metal material is providedin the wiring layer (which is composed solely of insulating material)along the dicing region is referred to as a non-metal containing area.Thus, the semiconductor layer in the non-metal containing area isscribed deeper than that in the metal containing area, which formsconcave portions in the trench and asperity or irregularity on thebottom of the trench or groove along the dicing region. The metalcontaining area and the non-metal containing area are provided in thedicing region where the substrate is diced in the thickness direction.

Also, in the laser-grooving step, the wiring or insulating layer islikely scribed to have a tapered shape in a cross section along thewidth direction. This may form another asperity on a side surface of thetrench due to the metal materials in the dicing regions. Furthermore,since the laser beam ablates the wiring layer close to the metalcontaining area less than the wiring layer close to the non-metalcontaining area, the former wiring layer has a tapered angle less thanthat of the latter wiring layer. In other words, when the wiring layerhas both of the non-metal containing area and the metal containing area,the width of the trench may vary along the dicing region.

The dicing step is carried by the Bosch process including a filmdepositing step and a film etching step, which are repeatedly carriedout. The Bosch process deposits a film on the bottom and side surfacesof the trench in the film depositing step, and removes the film on thebottom of the trench and then dig the exposed semiconductor layer in thedepth direction. The conditions of the film depositing step and the filmetching step are selected so that the film remains on the side surfaceof the trench, which allows the semiconductor layer to be etched in thedepth direction substantially perpendicular to the bottom. In otherwords, it is desired to form the layer having uniform thickness in thetrench during the film depositing step, in order to etch thesemiconductor layer in the depth direction and produce the element chipshaving ununiform configuration.

However, as discussed above, the asperity or irregularity in the trenchformed in the laser grooving step likely causes the layer in the trenchformed during the film depositing step have the inhomogeneous thickness.Thus, the produced element chips have the ununiform configuration,vertical-striped patterns on the side walls, and side-etched portions inthe interface between the semiconductor layer and the wiring layer. Thistends to deteriorate the appearance and the deflecting strength.Furthermore, the non-uniform width of the trench fails to stabilize thequality of the produced element chips.

In the meanwhile, as the laser grooving step causes the debris,typically before the dicing step, the cleaning step is carried out toremove the debris by etching or scribing. The cleaning step is madeunder a condition such that the most engrained debris, including forexample, the debris containing metal components and a substantial amountof the adhering debris can be removed (e.g., for an extended time).However, the material and the scattering of the debris caused in thenon-metal containing area and the metal containing area are differentfrom each other. For example, the debris containing much metal materialadheres to a region around the metal containing area. Thus, the cleaningstep under the aforementioned condition etches or scribes the trenchmore deeply in the non-metal containing area or the area other than themetal containing area. Thus, the asperity of the trench formed beforethe cleaning step is emphasized by the cleaning step.

To address this, the present embodiment has a step for melting thesemiconductor layer after forming the trench or unfinished trench in thelaser grooving step. The melted semiconductor layer planarizes thebottom of the trench without the asperity, which substantially enhancesthe reliability of the following plasma-etching step.

The laser grooving step may include a first step for irradiating a laserbeam (referred to as an ablation laser beam) onto the dicing regions toablate the resin layer and the wiring layer, and a second step for againirradiating a laser beam (referred to as a melting laser beam) onto thedicing regions to melt the exposed surface of the semiconductor layer.

In the second step, the melting laser beam irradiated to the trench hassuch an intensity enough to melt the semiconductor layer, but less toablate the exposed semiconductor layer on the bottom of the trench. Theexposed surface of the semiconductor layer on the bottom of the trenchhaving the asperity is melted or amorphous-alloyed to flow on andplanarizes the surface of the trench. Then, the melted semiconductorhardens to form a new flat layer on the bottom of the trench.

In the second step, the melting laser beam melts the semiconductor layerand also diffuses the debris adhering to the side wall of the trench. Atleast a portion of the diffused debris is absorbed and incorporatedwithin the melted semiconductor to form the new layer on the bottom ofthe trench. Thus, a localization of the debris is eliminated in thesecond step to homogenize the bottom of the trench. This allowsreduction of the time required for the cleaning step, and enhances theflatness of the bottom in the trench after the cleaning step.

Furthermore, in the second step, the wiring layer exposed on the sidewall of the trench is melted, which reduces the asperity thereon andimproves the verticality thereof. Also, the width of the trench isconstant so that the linearity is improved. Therefore, the plasmaprocess is achieved in a more reliable manner so that the producedelement chip gets better quality.

[First Embodiment] Referring to drawings, a manufacturing process of anelement chip will be described in detail hereinafter. FIG. 1 is aflowchart illustrating some steps of the manufacturing process accordingto a first embodiment of the present invention. FIG. 2A is a top planview of a substrate which is an object to be processed by the presentembodiment, and FIG. 2B is a cross-sectional view taken along a line X-Xof FIG. 2A. FIG. 3A is an enlarged top plan view schematicallyillustrating a portion of the substrate, in which a resin layer 103 isdepicted with dots, and FIG. 3B is a cross-sectional view taken along aline Y-Y of FIG. 3A.

1) Preparing Step: Firstly, a substrate 10 which is an object to beprocessed or diced is prepared (FIG. 1A). The substrate 10 has first andsecond sides 10X, 10Y, and includes a semiconductor layer 101, a circuitlayer 102 and a resin layer 103 stacked on the first side 10X thereof.Also, the substrate 10 contains dicing regions 110 and element regions120 each defined by the dicing regions 110.

A circuit layer such as a semiconductor circuitry, an electroniccomponent, and/or a MEMS (not shown) may be formed in the elementregions 120. The circuit layer 102 includes a test circuitry known as aTEG (Test Element Group) containing a metal material 104 such as copper(Cu) and aluminum (Al) in the dicing regions thereof.

The dicing regions 110 are not limited to straight lines in shape andmay have any configurations determined in accordance with the outline ofthe desired element chips 30 (shown in FIG. 2A), which may be a zig-zagline and a wavy line for example. Thus, the element chips 30 may have arectangular or hexagonal outline.

The dicing regions 110 has a width, which is not limited to particularone and may be selected appropriately in accordance with the size of thesubstrate 10 and the element chips 30. The dicing regions 110 may havethe width in a range between 10-300 μm, for example, and each of thedicing regions 110 may have the width same as or different from oneanother. Typically, the substrate 10 may contain a plurality of thedicing regions 110. A pitch between the adjacent dicing regions 110 isnot limited to particular one and may be designed appropriately inaccordance with the size of the substrate 10 and the element chips 30.

Also, the semiconductor layer 101 may be made of silicon (Si), galliumarsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC), forexample.

The wiring layer 102 may include a multi-stacked wiring layer containinglow-dielectric layers of a low-k material and wiring layers of copper(Cu), and also contain a variety of metals, insulating layers made ofmaterial such as silicon dioxide (SiO₂), silicon nitride (Si₃N₄),lithium tantalate (LiTaO₃), and lithium niobate (LiNbO₃). The wiringlayer 102 may further include electrode pads and bumps 102.

The resin layer 103 is formed to protect the element regions 120, whichmay contain so-called a resist material including a photoresist made of,for example, a thermosetting resin such as polyimide, a photoresist suchas a phenol resin, and a soluble resin such as polyvinyl alcohol andsoluble polyester resin, and a phenol resin. The resin layer 103 may beformed by, for example, forming a sheet of the resist material and thenattaching the sheet to the semiconductor layer 101 or to the wiringlayer 102 prior to formation of the resin layer 103, or by applying amaterial solution of the resist material to the semiconductor layer 101or to the wiring layer 102 prior to formation of the resin layer 103 bymeans of the spin-coating or spray-coating techniques.

2) Laser Grooving Step: In the laser grooving step, a laser beam isirradiated to the first side 10X of the substrate along the dicingregions 110 to form a plurality of trenches 111 (FIG. 4C) shallower thanthat of the substrate 10, which correspond to the dicing regions 110.During the laser grooving step, the substrate 10 may be held on aconveying carrier 20 (FIG. 9) as will be described later for easyhandling thereof.

The trench 111 may have a depth approximately same or close to that ofthe wiring layer 102 of the substrate 10. In particular, the depth ofthe trench 111 may be in a range between 80-120% of the wiring layer102, or in a range between 100-120% of the wiring layer 102. Thus, theresin layer 103 and all or most of the wiring layer 102 are removedalong the trench, and a portion of the semiconductor layer 101 is alsoremoved in the laser grooving step.

The laser grooving step according to the present embodiment includes afirst step and a second step. In the first step, an ablation laser beamLa is irradiated onto the resin layer 103 along the dicing regions 110to ablate the resin layer 103 and the wiring layer 102, thereby toexpose the semiconductor layer 101 in the dicing regions 110. In thesecond step, a melting laser beam Lm is irradiated onto the exposedsurface of the semiconductor layer 101 to planarize it along the dicingregions 110.

Referring to FIGS. 4A-4C, the laser grooving step will be describedherein in detail. FIGS. 4A-4C are schematic cross-sectional views of thesubstrate 10 showing the laser grooving step of the manufacturingprocess according to the present embodiment.

a) First Step: The substrate 10 is prepared (FIG. 4A), and ablationlaser beam La is irradiated onto the resin layer 103 of the substrate 10along the dicing regions 110 in the first step, which ablates the resinlayer 103 and almost all of the wiring layer 102, thereby to exposesemiconductor layer 101 in the dicing regions 110 (FIG. 4B).

The ablation laser beam La is irradiated under such a condition thatboth of the resin layer 103 and the wiring layer 102 are removed byablation. The ablation laser beam La for ablating the resin layer 103requires a beam intensity less than that for ablating the wiring layer102. Thus, the beam intensity Ia of the ablation laser beam La is setgreater than a threshold intensity (minimum intensity) TB required forablating the wiring layer 102 and also greater than a thresholdintensity (minimum intensity) TA required for ablating the resin layer103 (Ia>TB>TA). Typically, the threshold intensity TB of the ablationlaser beam La is greater than another threshold intensity (minimumintensity) TD required for ablating the semiconductor layer 101 (TB>TD).Thus, the ablation laser beam La used in the first step may ablate aportion of the semiconductor layer 101. The beam intensity Ia is definedas a central intensity of the ablation laser beam La. Other beamintensity Im, Ic, Ia1, and Ia2 are so defined accordingly.

As illustrated in FIGS. 4A and 4B, the dicing region 110 may have ametal containing area 110 a where a metal material 104 is provided inthe wiring layer 102 and a non-metal containing area where no metalmaterial 104 is provided in the wiring layer 102 (which is composedsolely of an insulating material). As shown, the ablation laser beam Lamay scribe or dig the semiconductor layer 101 deeper in the non-metalcontaining area 110 b than in the metal containing area 110 a, whichforms concave portions on the bottom surface of the trench 111 in thenon-metal containing area 110 b, thereby to make irregularity on thebottom surface of the trench 111.

The pulsed ablation laser beam La may be irradiated once (Na=1) or moresequences (Na≥2) repeatedly in the first step. When the pulsed ablationlaser beam La is repeatedly irradiated more sequences (Na≥2), eachirradiation sequence of the pulsed ablation laser beam La may be carriedout under the conditions same as or different from one another. Itshould be noted that the irradiation sequence is intended as the seriesof the scanned irradiation of the pulsed ablation laser beam La ratherthan the irradiation pulse numbers thereof.

The beam profile of the ablation laser beam La is not limited to aparticular one. That is, the beam profile of the ablation laser beam Lain the width direction may have a Gaussian distribution or a Top-hatdistribution. The Gaussian distribution is a normal distribution. Theintensity of the Top-hat distribution is almost the same across thewidth direction, and 90-98% even at shoulder ends in the Top-hatdistribution (where the intensity is rapidly falling down) relative tothe intensity at the central region. However, it is preferable that thebeam profile of the ablation laser beam La at least in the widthdirection has the Top-hat distribution. The intensity of the ablationlaser beam La having the Top-hat distribution can readily be increasedacross the width direction so as to ablate the wiring layer 102 with anintense power in an efficient manner.

b) Second Step: The melting laser beam Lm is irradiated onto the exposedsurface of the semiconductor layer 101 to melt it along the dicingregions 110 (FIG. 4C).

The melting laser beam Lm is irradiated under a condition such that thesemiconductor layer 101 is melted or fused. The beam intensity of themelting laser beam Lm is less than that of the ablation laser beam Laused in the first step. Thus, the actual intensity Im of the meltinglaser beam Lm should be equal to or more than a threshold intensity(minimum intensity) TC of the laser beam required for melting thesemiconductor layer 101 but less than the threshold intensity TDrequired for ablating the semiconductor layer 101 (TD>Im≥TC).

As discussed above, the threshold intensity TB of the ablation laserbeam La required for ablating the wiring layer 102 is greater than thethreshold intensity TD required for ablating the semiconductor layer 101(TB>TD). Meanwhile, the threshold intensity TD is greater than thethreshold intensity TC of the laser beam required for melting thesemiconductor layer 101 (TD>TC). Thus, the actual intensity Im of themelting laser beam Lm should be less than the intensity Ia of theablation laser beam La (Ia>Im). The relationship among the thresholdintensity and the beam intensity are expressed, for example, as:Ia>TB>TD>Im≥TC>TA.

The semiconductor layer 101 having the irregularities on the bottomsurface of the trench 111 is melted by irradiating the melting laserbeam Lm. The melted semiconductor in the non-metal containing area 110 bflows into and fills up with the concave portion on the bottom surfaceof the trench 111 so that a surface roughness thereon is reduced. Then,the melted semiconductor is hardened so that a flat layer is rebuilt onthe bottom surface of the trench 111. Thus, the surface roughness on thebottom surface of the trench 111 formed by the first step is reducedrelative to the surface roughness on the bottom surface of the trench111 processed by the second step. The surface roughness on the bottomsurface of the trench 111, which is measured in accordance with theJapanese Industrial Standards (JIS B 0601), may be adjusted to be equalto or less than 0.5 μm.

The debris on side walls of the trench 111 after the first step isdiffused with the power of the melting laser beam Lm during the secondstep, and at least some of the diffused debris is absorbed in the meltedsemiconductor and incorporated in the newly rebuilt layer on the bottomsurfaces of the trench 111. Also, the debris localized around the metalcontaining areas 110 a of the trench 111 after the first step are spreadacross the bottom surface of the trench 111 after the second step. Thus,the second step planarizes the bottom surface of the trench 111 and alsohomogenizes the composition of the rebuilt layer. This allows a cleaningstep to remove the debris in an efficient manner, and stabilize a plasmaprocess in the following dicing step.

The debris adhering onto the resin layer 103 in the element regions 120may be removed by cleaning the substrate 10 after the laser groovingstep or the dicing step. Alternatively, the debris adhering onto theresin layer 103 may be removed along with the resin layer 103 bycleaning or dissolving the resin layer 103 with a dissolving agent.Furthermore, the debris adhering onto the resin layer 103 may be removedtogether with the resin layer 103 by ashing the resin layer 103 afterthe dicing step.

The melting laser beam Lm may be irradiated once (Nm=1) or moresequences (Nm≥2) repeatedly in the second step. When the melting laserbeam Lm is repeatedly irradiated more sequences (Nm≥2), each irradiationsequence of the melting laser beam Lm may be carried out under theconditions same as or different from one another.

It is preferable that the beam profile of the melting laser beam Lm atleast in the width direction has the Top-hat distribution. The intensityof the melting laser beam Lm having the Top-hat distribution can readilybe increased even at the ends in the width direction so that thesemiconductor layer 101 is melted across the bottom surface of thetrench 111 in an efficient manner. This allows the trenches 111 eachhaving a uniform configuration.

Preferably, the irradiation width or beam width of the melting laserbeam Lm in the width direction of the dicing region 110 is designed tobe greater than that of the ablation laser beam La. In this instance,the tapered portion of the side wall of the trench 111 and/or theremaining portion that has not been scribed can be removed in a reliablemanner, thereby to achieve a uniform configuration of the trenches 111.The irradiation width of the laser beam corresponds to the length alongthe width direction of the dicing region 110 where the laser beam isirradiated. Typically, the irradiation width of the ablation laser beamLa is similar to or substantially the same as the width of the dicingregion 110.

FIG. 5 is a perspective view schematically illustrating a structure of alaser processing machine 300 used for the laser grooving step of theembodiment. The laser processing machine 300 includes, for example, alaser oscillator 301, a collimating lens 302, a mask 303, a beam bender304, and a collecting lens 305. The laser beam L emitted from the laseroscillator 301 is irradiated onto the collimating lens 302 which adjustsa diameter of the laser beam L to one appropriate for the mask 303. Thelaser beam L through the collimating lens 302 is then irradiated ontothe mask 303 which shapes the laser beam to have the beam diametercorresponding to the width of the dicing region 110 on the substrate 10.The laser beam L through the mask 303 is then reflected at the beambender 304 to the collecting lens 305 and the substrate 10.

The laser beam L having the Top-hat distribution may be shaped byoptically shaping the laser beam having the Gaussian distribution, forexample, by means of a Diffractive Optical Element (DOE) or anaspherical beam shaper.

The laser oscillator 301 may preferably be a pulsed-laser oscillatoroscillating a pulsed laser beam. This is because the pulsed laser beamgives less thermal impact on the substrate 10 than the continuous-wavelaser beam. The mechanism for oscillating the pulsed-wave laser beam isnot limited to a particular one, and the pulsed-wave laser oscillator301 may adapt various mechanisms, which mechanically shutters the laserbeam ON and OFF, controls an optical source of the laser beam L to beexcited intermittently, or optically switches the laser beam L outputtherefrom, for example. The type of the laser oscillator 301 is notlimited to a particular one, and may be a semiconductor laser oscillatorusing a semiconductor material as a laser media for laser oscillation, agas laser oscillator using a gas such as carbon dioxide (CO₂) as thelaser media, a solid laser oscillator using a solid material such as YAGas the laser media, and a fiber laser oscillator, for example. One ormore of those laser oscillators may be adapted individually or incombination.

Although a pulse width of the laser beam L irradiated onto the substrate10 is not limited to a particular one, it may preferably be 500 ns orless, more preferably 200 ns or less, in order to reduce the thermalimpact thereto. Also, although not limited thereto, a peak wavelength ofthe laser beam L may preferably be in an ultra-violet region (having thepeak wavelength between about 200 nm and about 400 nm) to increase anabsorption of the laser beam L to the substrate. Furthermore, althoughnot limited thereto, a frequency of the laser beam L may be betweenabout 1 kHz and 200 kHz, preferably between about 10 kHz and 300 kHz.Thus, the higher frequency allows the higher rate processing.

FIG. 6A is a photograph depicting the top side of the substrate 10 afterthe first step. In the first step, the ablation laser beam La was used,which has the Top-hat distribution of the beam diameter of 14.5 thefrequency of 60 kHz, and the pulsed energy of 7.5 μJ. The ablation laserbeam La was twice scanned along two irradiation preset-lines spaced awayfrom each other by 10 μm in the width direction of the dicing region110, at a scanning rate of 90 mm/s.

FIG. 6B is a photograph depicting the top side of the substrate 10 afterthe second step. In the second step, the melting laser beam Lm was used,which has the Top-hat distribution of the beam diameter of 14.5 thefrequency of 200 kHz, and the pulsed energy of 2.5 μJ. The melting laserbeam Lm was once scanned along the two irradiation preset-lines spacedaway from each other by 10 μm in the width direction of the dicingregion 110, at the scanning rate of 200 mm/s.

The photograph of FIG. 6A after the first step shows the dicing region110 having many portions which appear relatively dark. This isconsidered as a result of a diffused scattering of the illuminationlight at fine asperity left in the dicing region 110. On the other hand,the photograph of FIG. 6B after the second step shows the dicing region110 having many portions which are brighter than those of FIG. 6A. Thisis considered as a result of the flattened dicing region 110 and areduction of the diffused scattering of the illumination light.

3) Cleaning Step: A cleaning step for removing the debris left on thetrench 111 may be carried out after the laser grooving step before thedicing step, which facilitates the plasma processing to be implementedin a more stable and/or reliable manner.

The cleaning step may be carried out by irradiating a cleaning laserbeam, of which beam intensity is such that the debris left on the trench111 is removed. Typically, the beam intensity Ic of the cleaning laserbeam is greater than the beam intensity Im of the melting laser beam Lm.For example, the beam intensity Ic of the cleaning laser beam may bemore or less equal to the threshold intensity TB of the ablation laserbeam La required for ablating the wiring layer 102. To improve thecleaning efficiency, the scanning pitch (or the scanning rate) of thecleaning laser beam is preferably set greater than that of the laserbeam in the laser grooving step.

To increase the beam intensity Ic of the cleaning laser beam greaterthan the threshold intensity TB, it is preferable to irradiate the laserbeam (the second melting laser beam) having the beam intensity more orless equal to one of the melting laser beam Lm after irradiating thecleaning laser beam. This allows the bottom surface of the trench 111 tobe planarized again even if the cleaning laser beam forms theirregularity thereon.

In the cleaning step, the cleaning laser beam may be used, which has theTop-hat distribution of the beam diameter of 14.5 the frequency of 60kHz, and the pulsed energy of 7.5 μJ. The cleaning laser beam may beonce or twice scanned along the two irradiation preset-lines spaced awayfrom each other by 10 μm in the width direction of the dicing region110, at the scanning rate of 600 mm/s.

FIG. 7 is a photograph depicting the top side of the substrate 10 afterirradiating the cleaning laser beam and the second melting laser beamunder the irradiation conditions as described above. When comparing thedicing regions 110 shown in the photographs of FIG. 6B and FIG. 7, thedicing region 110 of FIG. 7 has more portions which appear bright thanthat of FIG. 6B. This is the result of the cleaning step which furthermakes the bottom surface in the dicing region 110 even flatter.

The cleaning laser beam may be irradiated once (Nc=1) or more sequences(Nc≥2) repeatedly. When the cleaning laser beam is repeatedly irradiatedmore sequences (Nc≥2), each irradiation sequence of the cleaning laserbeam may be carried out under the conditions same as or different fromone another. The cleaning laser beam have the beam intensity and thebeam profile which are not limited to particular ones, and may have theGaussian distribution or the Top-hat distribution, for example.

The cleaning step may be carried out by the plasma process. The plasmaatmosphere for cleaning the trenches 111 may be generated under thecondition different from one for dicing the substrate 10. The plasmaprocess in the cleaning step preferably uses the source gases forremoving the components of the semiconductor layer 101 such as siliconand silicon oxide.

The plasma cleaning step may be carried out for about 1-2 minutes in theplasma atmosphere generated within a plasma processing apparatus as willbe described hereinafter, by applying an antenna with the high-frequencypower of 1000-2000 W while supplying a mixed gas of SF₆ and O₂ at a rateof 200 sccm to have the pressure of 5 Pa in the vacuum chamber 203.Also, a high-frequency electrode provided with a stage may be appliedwith the high-frequency power of about 150 W to increase the removingefficiency of the debris.

4) Dicing Step: Next, referring to FIGS. 8A and 8B, a dicing step willbe described herein. FIGS. 8A and 8B are cross sectional viewsschematically depicting a portion of the substrate 10 in the dicingstep.

The substrate 10 having the trenches 111 formed thereon is exposedwithin the plasma atmosphere to etch the remaining portion in the depthdirection along the dicing region 110, thereby to dice or separate thesubstrate 10 into a plurality of element chips 30 each having theelement regions 120. The resin layer 103 provided uppermost over thesubstrate 10 performs a function as a mask for protecting the elementregions 120.

The dicing step may preferably be carried out with the substrate 10being held on the base material 22 for ease of handling thereof. Thebase material 22 adheres onto the second side 10Y of the substrate 10.Although the base material 22 is not limited to a particular one, as thesubstrate 10 is subjected to be diced with the base material 22 thereon,it is preferably made of a flexible resin film to facilitate each of thediced element chips 30 to be readily picked up from the base material22. Also, as depicted in FIG. 9, the base material 22 is held on a frame21 for easy handling thereof. The present disclosure may refer the frame21 and the base material 22 held thereon collectively as a conveyingcarrier 20. FIG. 9A is a top plan view of the conveying carrier 20 andthe substrate 10 held on the base material 22, and FIG. 9B is a crosssectional view taken along a line Z-Z of FIG. 9A.

Although the resin film may be made of any material, it may be made of athermoplastic resin including, for example, polyethylene, polyolefinsuch as polypropylene, and polyester such as polyethylene terephthalate.The resin film may contain various additives including, for example, arubber component for adding the stretching property (for example,ethylene-propylene rubber (EPM), ethylene-propylene-diene rubber(EPDM)), a plasticizer, a softener, an antioxidant, and a conductivematerial. Also, the thermoplastic resin may contain a functional groupshowing a photopolymerization reaction such as an acryl group.

The base material 22 includes an upper side 22 a (an adhesive side)having an adhesive thereon and a lower side 22 b (a non-adhesive side 22b) having no adhesive thereon. The periphery of the adhesive side 22 aadheres to the bottom side of the frame 21 and the base material 22covers an opening of the frame 21. An exposed portion in the opening ofthe adhesive side 22 a adheres to the second side 10Y of the substrate10. During the plasma process, the base material 22 is seated on aplasma processing stage (which is referred to simply as a stage) so thatthe non-adhesive side 22 b is in contact with the stage.

The adhesive side 22 a preferably contains an adhesive material of whichadhesibility is weakened with an ultra-violet beam (UV-radiation). Thisallows each of the diced element chips obtained after the plasma-dicingstep to easily be peeled off and picked up from the adhesive side 22 awith the UV-radiation. The base material 22 may be formed, for example,by applying an UV-curing acrylic adhesive on the adhesive side 22 a ofthe resin film to have a thickness of 5-20 μm.

The frame 21 contains the opening of an area equal to or more than thewhole substrate 10, and has a predetermined width and a substantiallyconstant thickness. Also, the frame 21 has such a rigidity that it canbe transferred or delivered with the base material 22 and the substrate10 adhering thereto. Although the shape of the opening of the frame 2 isnot limited to a particular one, it may be in a shape of a circle, apolygon such as a rectangle and a hexagon. The frame 21 may be providedwith a notch 21 a and/or a corner cut 21 b for alignment thereof. Also,the frame 2 may be formed of, for example, a metal such as aluminum andstainless steel, or a resin.

Next, referring to FIG. 10, a plasma processing apparatus 200 used in aplasma-dicing step will be described in detail hereinafter, although itis not limited thereto. FIG. 10 depicts a schematic structure in a crosssection of the plasma processing apparatus 200 used in the presentembodiment.

The plasma processing apparatus 200 includes a stage 211, on which theconveying carrier 20 is seated so that the adhesive side 22 a of thebase material 22 (which adheres to and supports the substrate 10) facesupwardly. Arranged over the stage 211 is a cover 224 which covers atleast a portion of the frame 21 and the base material 22 and includes awindow 224W exposing at least a portion of the substrate 10. The cover224 is provided with a biasing member 207 for biasing the frame 21downwardly when the frame 2 is seated on the stage 211. The biasingmember 207 may preferably be a component such as a coil spring and anelastic resin for achieving a point contact with the frame 21. Thisrestricts a thermal communication between the frame 21 and the cover224, and also allows correcting a distortion of the frame 21.

The stage 211 and the cover 224 are received in a reaction chamber (avacuum chamber) 203. The vacuum chamber 203 is shaped in a substantiallycylindrical configuration having an opening at the top thereof, which isclosed by a dielectric member 208 formed as a lid of the vacuum chamber203. The vacuum chamber 203 may be formed of aluminum, stainless steel(SUS), or aluminum with anodic oxide coating, for example. Thedielectric member 208 may be formed of yttrium oxide (Y₂O₃), aluminumnitride (AlN), alumina (Al₂O₃), or quartz (SiO₂), for example. Arrangedon or above the dielectric member 208 is a top or first electrode 209.The first electrode 209 is electrically connected to a firsthigh-frequency power source 210A. The stage 211 is positioned at thebottom side in the vacuum chamber 203.

The vacuum chamber 203 is provided with a gas inlet 203 a forintroducing a gas and a gas outlet 203 b for exhausting the gas. The gasinlet 203 a is configured to be connected selectively to one of amaterial gas source such as a processing gas source 212 and an ashinggas source 213 each through a conduit. The outlet 203 b is connected toa decompressing mechanism 214 having a vacuum pump for exhausting a gaswithin the vacuum chamber 203 and decompressing it.

The stage 211 includes an electrode layer 215, a metal layer 216, and abase member 217 supporting the electrode layer 215 and the metal layer216, each having a substantially circular shape. The stage 211 alsoincludes a peripheral member 218 surrounding the electrode layer 215,the metal layer 216, and the base member 217. The peripheral member 218is formed of a metal having a conductivity and an etching resistance forprotecting the electrode layer 215, the metal layer 216, and the basemember 217 from the plasma exposure. Provided on an upper surface of theperipheral member 218 is an annular circumferential ring 229 forprotecting it from the plasma exposure. The electrode layer 215 and thecircumferential ring 229 may be formed of the dielectric material aslisted above.

Arranged within the electrode layer 215 are a first or electrostaticchuck (ESC) electrode 219 and a second or high-frequency electrode 220electrically connected to a second high-frequency power source 210B. TheESC electrode 219 is electrically connected to a DC power source 226.The electrostatic chucking mechanism is composed of the ESC electrode219 and the DC power source 226.

The metal layer 216 may be formed of aluminum with an anodic oxidationcoating, for example. The metal layer 216 contains a coolant channel 227configured to cool the stage 211. Cooling the stage 211 causes the basematerial 22 on the stage 211 cooled down, as well as the cover 224 whoseportion contacts with the stage 211. This protects the substrate 10 andthe base material 22 from being damaged due to a heat applied during theplasma processing step. A coolant in the coolant channel 227 iscirculated by a coolant circulation apparatus 225.

Provided around the peripheral portion of the stage 211 is a pluralityof supporting members 222 extending therethrough. Each of the supportingmembers 222 supports the frame 21 of the conveying carrier 20. Thesupporting members 222 are driven by a lifting mechanism 223A to moveupward and downward. The conveying carrier 20 is delivered into thevacuum chamber 203, and passed on the supporting members 222 which hasbeen raised at a given level. Then the supporting members 222 arelowered with the top surface being flush with or lower than the stage211, which sets the conveying carrier 20 on the stage 211 at apredetermined position thereof.

Also, a plurality of lifting rods 221 are coupled to the peripheral edgeof the cover 224 for moving it upward and downward. The lifting rods 221are driven by another lifting mechanism 223B. The operation of thelifting mechanisms 223A, 223B can be controlled independently eachother.

The controller 228 is configured to control operations of the plasmaprocessing apparatus 200 which includes the first high-frequency powersource 210A, the second high-frequency power source 210B, the processinggas source 212, the ashing gas source 213, the decompressing mechanism214, the coolant circulation apparatus 225, the lifting mechanisms 223A,223B, and the electrostatic chucking mechanism.

The plasma atmosphere is generated under the condition suitable foretching the remaining portion (mostly the semiconductor layer 101) ofthe substrate 10. The condition is selected appropriately in accordancewith the material of the semiconductor layer 101. When the semiconductorlayer 101 is made of silicon, the Bosch process may be used to etch thesemiconductor layer 101 along the dicing region or groove. The Boschprocess includes a film depositing step, a film etching step, and asilicon etching step in series which are repeated to etch or dig thesemiconductor layer 101 in the depth direction.

The film depositing step is carried out under the condition wheresupplying a source gas of C₄H₈ at a rate of 150-250 sccm to have thepressure in the vacuum chamber 203 controlled between 5-15 Pa, theantennas 209 is applied with the first high-frequency power of 1500-2500W, while the high-frequency electrode 220 is applied with the secondhigh-frequency power of 0 W, for 5-15 seconds.

The film etching step is carried out under the condition where supplyinga source gas of SF₆ at a rate of 200-400 sccm to have the pressure inthe vacuum chamber 203 controlled between 5-15 Pa, the antennas 209 isapplied with the first high-frequency power of 1500-2500 W, while thehigh-frequency electrode 220 is applied with the second high-frequencypower of 100-300 W, for 2-10 seconds.

The silicon etching step is carried out under the condition wheresupplying a source gas of SF₆ at a rate of 200-400 sccm to have thepressure in the vacuum chamber 203 controlled between 5-15 Pa, theantennas 209 is applied with the first high-frequency power of 1500-2500W, while the high-frequency electrode 220 is applied with the secondhigh-frequency power of 50-200 W, for 10-20 seconds.

The film depositing step, the film etching step, and the silicon etchingstep are repeatedly carried out under the aforementioned conditions sothat each of the grooves can be etched in the vertical or depthdirection at a rate of 10 μm per minute. Several types of the sourcegases may be used together for generation of the plasma atmosphere. Inthis instance, those source gases may be introduced in the vacuumchamber 203 in series with time lags or may be mixed and introduced inthe vacuum chamber 203.

As described above, the substrate 10 is diced into a plurality of theelement chips 30 each having the element regions 120 while the substrate10 is held on the base material 22 (FIG. 8A). After the dicing step, aplurality of the element chips 30 held on the base material 22 aredelivered to a pick-up step, in which each of the element chips 30 isdetached or picked up from the base material 22 to obtain the separateelement chips 30.

Also, after the dicing step, the resin layer 103 remaining on theelement chips 30 may be removed by ashing or cleaning step (FIG. 8B). Inthis case, the debris, which adhere to the resin layer 103 in theelement regions 120 during the laser grooving step, can be removedtogether with the resin layer 103.

[Second Embodiment] The manufacturing process of the element chipaccording to the second embodiment is similar to one of the firstembodiment except that the first step of the laser grooving stepincludes a first ablation step for ablating the resin layer and a secondablation step for ablating the wiring layer. FIG. 11 is a flowchartillustrating some steps of the manufacturing process of the element chipaccording to the second embodiment, and FIGS. 12A-12D are schematiccross-sectional views of the substrate showing the laser grooving stepof the manufacturing process according to the second embodiment.

a) First Ablation Step: A first ablation laser beam La1 is irradiatedonto the resin layer along the dicing region 110 of the substrate 10(FIG. 12A) to expose the wiring layer 102 (FIG. 12B).

The first ablation laser beam La1 is irradiated under such a conditionto ablate the resin layer 103. Typically, the ablation laser beam forablating the resin layer 103 requires a beam intensity less than thatfor ablating the wiring layer 102. Thus, the intensity Ia1 of the firstablation laser beam La1 is set greater than a threshold intensity(minimum intensity) TA required for ablating the resin layer 103 butless than the threshold intensity (minimum intensity) TB required forablating the wiring layer 102 (TB>Ia1>TA).

The first ablation laser beam La1 may be irradiated once (Na₁=1) or moresequences (Na₁≥2) repeatedly in the first ablation step. When the firstablation laser beam La1 is repeatedly irradiated more sequences (Na₁≥2),each irradiation sequence of the first ablation laser beam La1 may becarried out under the conditions same as or different from one another.It should be noted that the irradiation sequence is intended as theseries of the scanned irradiation of the ablation laser beam La1 ratherthan the irradiation pulse numbers thereof.

The beam profile of the first ablation laser beam La1 is not limited toa particular one. That is, the beam profile of the first ablation laserbeam La1 in the width direction may have a Gaussian distribution or aTop-hat distribution. The Gaussian distribution is a normaldistribution. The intensity of the Top-hat distribution is almost thesame across the width direction.

b) Second Ablation Step: A second ablation laser beam La2 is irradiatedonto the wiring layer 102 along the dicing region 110 of the substrate10 (FIG. 12B) to expose the semiconductor layer 101 (FIG. 12C). Most orall of the wiring layer 102 along the dicing region 110 are removed inthe second ablation step so that the semiconductor layer 101 is exposedacross the bottom surface of the trench 111.

The second ablation laser beam La2 is irradiated under such a conditionto ablate the wiring layer 102. The intensity Ia2 of the second ablationlaser beam La2 is set greater than a threshold intensity (minimumintensity) TB required for ablating the wiring layer 102 (Ia2>TB).Typically, the threshold intensity TB is greater than that required forablating the semiconductor layer 101 (TB>TD). Therefore, the secondablation step may ablate a portion of the semiconductor layer 101 alongwith the wiring layer 102.

As illustrated in FIG. 12C, the second ablation laser beam La2 mayscribe or dig the semiconductor layer 101 deeper in the non-metalcontaining area 110 b where no metal material 104 is provided in thewiring layer 102, than in the metal containing area 110 a where themetal material 104 is provided in the wiring layer 102. This formsconcave portions on the bottom surface of the trench 111 in thenon-metal containing area 110 b, thereby to make irregularity on thebottom surface of the trench 111.

The second ablation laser beam La2 may be irradiated once (Na₂=1) ormore sequences (Na₂≥2) repeatedly in the second ablation step. When thesecond ablation laser beam La2 is repeatedly irradiated more sequences(Na₂≥2), each irradiation sequence of the second ablation laser beam La2may be carried out under the conditions same as or different from oneanother.

Although the beam profile of the second ablation laser beam La2 is notlimited to a particular one, preferably it has the Top-hat distributionat least in the width direction. While the high power is required forablating the wiring layer 102, the second ablation laser beam La2 havingthe Top-hat distribution can remove the wiring layer 102 in an efficientmanner.

c) Second Step: The melting laser beam Lm is irradiated onto the exposedsemiconductor layer 101 to melt it along the dicing region 110 (FIG.12D).

The intensity of the melting laser beam Lm is less than that of thesecond ablation laser beam La2 used in the second ablation step, andgreater than that of the first ablation laser beam La1 used in the firstablation step (Ia2>Im≥Ia1). Thus, a following relationship is satisfiedamong the threshold intensities and the beam intensities,Ia2>TB>TD>Im≥TC>Ia1>TA.

Preferably, the irradiation width of the melting laser beam Lm in thewidth direction across the dicing region 110 is greater than that of thesecond ablation laser beam La2. In this instance, the tapered portion ofthe side wall of the trench 111 and/or the remaining portion that hasnot been scribed are removed in an efficient or reliable manner, therebyto form a uniform configuration of the trench 111. Typically, theirradiation width of the second ablation laser beam La2 is similar to orsubstantially the same as the width of the dicing region 110.

[Third Embodiment] The manufacturing process of the element chipaccording to the third embodiment is similar to one of the secondembodiment except that after the first ablation step, a combination ofthe second ablation step and the second step is repeated multiple timesin the laser grooving step. FIG. 13 is a flowchart illustrating somesteps of the manufacturing process of the element chip according to thethird embodiment. The manufacturing process according to the thirdembodiment removes the wiring layer while planarizing the bottom surfaceof an incomplete or unfinished trench 111 formed by the second ablationstep and enhancing a perpendicularity of the side wall thereof, therebyto form a uniform configuration of the complete trench 111.

The second ablation step and the second step may be repeated multipletimes (not particular times, for example, a predetermined number oftimes) until a desired condition is satisfied. Alternatively, the secondablation step and the second step may be repeated until the bottomsurface of the incomplete or unfinished trench is planarized to be adesired condition. In each combination of the second ablation step andthe second step, the laser beam may be irradiated once or more times.

[Fourth Embodiment] In the fourth embodiment, the melting laser beam Lmis irradiated multiple times (Nm≥2) in the second step along theirradiation preset-lines, each of which is spaced away from another onein the width direction and extends in the longitudinal direction of thedicing region 110. Besides, the manufacturing process according to thefourth embodiment is similar to that of the second embodiment. FIG. 14is a top plan view schematically depicting a portion of the substrate 10in the second step according to the fourth embodiment.

The melting laser beam Lm is shaped to have the beam width W in thewidth direction narrower than the width of the dicing region 110, and adistance Wy between two of the adjacent irradiation preset-lines (e.g.,between irradiation preset-lines Y3 and Y1 and between irradiationpreset-lines Y2 and Y1) are defined as narrower than the beam width W.This achieves some irradiation regions on which the melting laser beamLm irradiated along the multiple irradiation preset-lines overlap oneanother, which efficiently planarizes the bottom surface of the trench111. Also, the first ablation laser beam La1 and the second ablationlaser beam La2 may be irradiated along the multiple irradiationpreset-lines, so that some irradiation regions of the laser beams La1,La2 overlap each other.

The debris may be caused even by the melting laser beam Lm. Such debrislikely adhere outside the irradiation regions of the melting laser beamLm. For example, when the melting laser beam Lm is irradiated on amiddle portion of the dicing region 110 (or the trench 111) along theirradiation preset-line Y1, the debris may likely adhere to both sidesin the width direction. Similarly, when the melting laser beam Lm isirradiated on the side portions of the dicing region 110, the debris maylikely adhere to the middle portion in the width direction.

According to the present embodiment, the melting laser beam Lm havingthe small beam width are irradiated multiple times along three of theirradiation preset-lines Y1, Y2, Y3, in which the melting laser beam Lmis lastly irradiated on either one of the side portions of the dicingregion 110, for example, along the irradiation preset-line Y3. In thisinstance, the debris caused by the last irradiation likely adhere to themiddle portion of the dicing region 110. However, the semiconductorlayer 101 in the middle portion of the trench 111 is readily etched inthe following cleaning step and the plasma processing step so that thedebris is also easily removed. The second last irradiation of themelting laser beam Lm is made on another one of the side portions of thedicing region 110, for example, along the irradiation preset-line Y2 inFIG. 14, which also likely causes the debris in the middle portion. Atleast a portion of the debris caused by the melting laser beam Lm priorto the last irradiation may be removed by the melting laser beam Lmirradiated prior to the last one.

In particular, the melting laser beam Lm is irradiated in a followingmanner. Firstly, the melting laser beam Lm is irradiated in the middleportion of the dicing region 110 along the irradiation preset-line Y1.Next, the melting laser beam Lm is irradiated in one side portion of thedicing region 110 along the irradiation preset-line Y2. Lastly, themelting laser beam Lm is irradiated in another side portion of thedicing region 110 along the irradiation preset-line Y3.

Although FIG. 14 depicts three of the irradiation preset-lines in thewidth direction along the dicing region 110, the number of theirradiation preset-lines is not limited thereto. Even if the meltinglaser beam Lm is irradiated along four or more of the irradiationpreset-lines in the width direction of the dicing region 110, the lastirradiation is made along the irradiation preset-line closest to oneside portion of the dicing region 110. FIG. 14 depicts the beam width Wof the melting laser beam Lm irradiated along the irradiationpreset-line Y1.

The manufacturing processes of the element chips according to thepresent invention are useful to achieve the desired plasma-dicing step,thereby to produce the elements chips from various types of thesubstrates.

[Reference Numerals] 10: substrate, 10X: first side (top side), 10Y:second side (bottom side), 101: semiconductor layer, 102: wiring layer,102 a: low-k material, 102 b: metal wire, 102 c: bump, 103: resin layer,104: metal material, 110: dicing region, 110 a: metal containing area,110 b: non-metal containing area, 111: trench, 120: element region, 20:conveying carrier, 21: frame, 21 a: notch, 21 b: corner cut, 22: basematerial, 22 a: adhesive side, 22 b: non-adhesive side, 30: elementchip, 200: plasma processing apparatus, 203: vacuum chamber, 203 a: gasinlet, 203 b: gas outlet, 207: biasing member, 208: dielectric member,209: antenna, 210A: first high-frequency power source, 210B: secondhigh-frequency power source, 211: stage, 212: processing gas source,213: ashing gas source, 214: decompressing mechanism, 215: electrodelayer, 216: metal layer, 217: base member, 218: peripheral member, 219:ESC electrode, 220: high-frequency electrode, 221: lifting rod, 222:supporting rod, 223A, 223B: lifting mechanism, 224: cover, 224W: window,225: coolant circulation apparatus, 226: DC power source, 227: coolantchannel, 228: controller, 229: circumferential ring, 300: laserprocessing machine, 301: laser oscillator, 302: collimating lens, 303:mask, 304: beam bender, 305: collecting lens

What is claimed is:
 1. A manufacturing process of an element chip,comprising: a preparing step for preparing a substrate having first andsecond sides opposed to each other, the substrate containing asemiconductor layer, a wiring layer and a resin layer formed on thefirst side, and the substrate including a plurality of dicing regionsand element regions defined by the dicing regions; a laser grooving stepfor irradiating a laser beam onto the dicing regions to form grooves soas to expose the semiconductor layer along the dicing regions; and adicing step for plasma-etching the semiconductor layer along the dicingregions through the second side to divide the substrate into a pluralityof the element chips, the laser grooving step comprising first andsecond steps, wherein the first step includes irradiating an ablationlaser beam to ablate the resin layer and the wiring layer so as toexpose the semiconductor layer along the dicing regions, and wherein thesecond step includes irradiating a melting laser beam to melt a surfaceof the semiconductor layer exposed along the dicing regions after thefirst step, wherein a beam intensity Ia of the ablation laser beam and abeam intensity Im of the melting laser beam satisfy Ia >Im.
 2. Themanufacturing process of the element chip according to claim 1, whereinthe beam intensity Im of the melting laser beam is less than a thresholdTD of a beam intensity required for ablating the semiconductor layer. 3.The manufacturing process of the element chip according to claim 1,wherein when TA is defined as a threshold of a beam intensity requiredfor ablating the resin layer, TB is defined as a threshold of a beamintensity required for ablating the wiring layer, TC is defined as athreshold of a beam intensity required for melting the semiconductorlayer, and TD is defined as a threshold of a beam intensity required forablating the semiconductor layer, a following relationship is satisfied,TB >TD >TC >TA, and wherein a following relationship is satisfied,TD >Im ≥TC.
 4. The manufacturing process of the element chip accordingto claim 1, wherein a beam profile of the melting laser beam in a widthdirection of the dicing region has a Top-hat distribution.
 5. Themanufacturing process of the element chip according to claim 1, whereinan irradiation width of the melting laser beam in a width direction ofthe dicing region is greater than that of the ablation laser beam. 6.The manufacturing process of the element chip according to claim 1,wherein a beam width of the melting laser beam in a width direction ofthe dicing region is less than a width of the dicing region, wherein themelting laser beam is irradiated multiple times in the second step alonga plurality of irradiation preset-lines, each of which is spaced away bya predetermined distance from adjacent one in the width direction andextends in a longitudinal direction of the dicing region, and whereinthe predetermined distance between the adjacent irradiation preset-linesis less than the beam width.
 7. The manufacturing process of the elementchip according to claim 6, wherein the melting laser beam is irradiatedmultiple times in the second step along three or more irradiationpreset-lines, and wherein the last irradiation of the melting laser beamis made along the irradiation preset-line closest to one side portion ofthe dicing region.